The present invention relates to a layout technology for semiconductor devices and particularly to the technology which can be adapted effectively for a semiconductor device including a nonvolatile memory.
In these years, a semiconductor device tends to load a non-volatile memory such as a large capacity flash memory with rapid progress in high integration density and function of a single chip semiconductor device.
For example, a microcomputer for keyboard control comprises a non-volatile memory in the capacity of about 1 MB in order to store the system BIOS (Basic Input/Output System).
Such large capacity non-volatile memory occupies about 50% or more of the chip layout area, and therefore, when it is required to layout such memory into a semiconductor chip, such non-volatile memories are combined into the limited chip area to realize efficient arrangement thereof.
Moreover, a layout design data is introduced into a certain stacked package. Namely, in view of saving time and labor required for design and development in the type of devices if a change is newly generated in development in a type of chip, an input/output circuit unit and a pad of one chip among two chips to be loaded into a stacked package are separated from each other, and the input/output circuit unit is included within the circuit having the intrinsic specifications of the chips. (For example, refer to the Patent Document 1.)
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2002-43531.